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Alif Semiconductor /AE302F80F5582AE_CM55_HE_View /LPGPIO /GPIO_LS_SYNC

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Interpret as GPIO_LS_SYNC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)GPIO_LS_SYNC

GPIO_LS_SYNC=Val_0x0

Description

Synchronization Level Register

Fields

GPIO_LS_SYNC

Writing a 1 to this bit results in all level-sensitive interrupts being synchronized to PCLK_INTR. They are not synchronized to PCLK_INTR by default.

0 (Val_0x0): No synchronization to PCLK_INTR

1 (Val_0x1): Synchronize to PCLK_INTR

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data